A memory device and associated techniques for reducing memory cell read disturbance during a scan process. The drain-end selection transistors of unselected sub-blocks are temporarily rendered conductive during the startup of the unselected word line voltages for a period of time to reduce the amount of capacitive coupling of the respective memory chain channel. This reduces a channel gradient that may be present in the memory chain channels, which also reduces the reading interference. Furthermore, the period of time is longer when the selected word line is in a source end or midrange subset of the word lines than when the selected word line is in a drain end subset of the word lines. Another option includes omitting the injection disturbance countermeasure or providing a less severe injection disturbance countermeasure if the unselected sub-blocks are not programmed.
展开▼