Spatial characterization of hot carriers injected into the gate dielectric stack of a MOSFET based non-volatile memory device

摘要

Subthreshold slope degradation in the NROM/spl trade/ localized-charge-trapping non-volatile memory device is utilized to investigate the spatial distributions of hot carriers injected into the gate dielectric stack. An analytical model is presented, which attributes the subthreshold slope degradation to the formation of a fringing field induced extended depletion layer. It is shown that electron and hole trapping takes place mostly in a narrow, 40-50 nm wide, region near the drain junction.