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Memory cell e.g. non-volatile two-bit-Trapping layer-memory cell, operating method for e.g. memory card, involves applying voltage between gate electrode and substrate section such that charge carrier is injected into memory element
Memory cell e.g. non-volatile two-bit-Trapping layer-memory cell, operating method for e.g. memory card, involves applying voltage between gate electrode and substrate section such that charge carrier is injected into memory element
The method involves applying a voltage to p-n junctions (114, 124) among a source region (112), a drain region (122) and a substrate section (130) such that an avalanche breakdown takes place at the respective p-n junction. Another voltage is applied between a gate electrode (170) and the substrate section such that a charge carrier (132) produced by the avalanche breakdown and injected into the substrate section is injected into a memory element that is arranged between the substrate section and the gate electrode. Independent claims are also included for the following: (1) a method for programming a memory cell (2) a method for deleting a memory cell (3) a semiconductor component with memory cells (4) an electronic system comprising the semiconductor component.
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