Embodiments herein describe techniques for a semiconductor device comprising an SRAM device having a plurality of SRAM memory cells and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is designed to supply power in parallel to the multiple SRAM memory cells of the SRAM device for a period of time. Other embodiments may be described and / or claimed.
展开▼