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Compiler-managed memory system for software-exposed architectures

机译:用于软件暴露架构的编译器管理的内存系统

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摘要

Microprocessors must exploit both instruction-level parallelism (ILP) and memory parallelism for high performance. Sophisticated techniques for ILP have boosted the ability of modern-day microprocessors to exploit ILP when available. Unfortunately, improvements in memory parallelism in microprocessors have lagged behind. This thesis explains why memory parallelism is hard to exploit in microprocessors and advocate bank-exposed architectures as an effective way to exploit more memory parallelism. Bank exposed architectures are a kind of software-exposed architecture: one in which the low level details of the hardware are visible to the software. In a bank-exposed architecture, the memory banks are visible to the software, enabling the compiler to exploit a high degree of memory parallelism in addition to ILP. Bank-exposed architectures can be employed by general-purpose processors, and by embedded chips, such as those used for digital-signal processing. This thesis presents Maps, an enabling compiler technology for bank-exposed architectures. Maps solves the problem of bank-disambiguation, i.e., how to distribute data in sequential programs among several banks to best exploit memory parallelism, while retaining the ability to disambiguate each data reference to a particular bank. Two methods for bank disambiguation are presented: equivalence-class unification and modulo unrolling. Taking a sequential program as input, a bank-disambiguation method produces two outputs: first, a distribution of each program object among the memory banks; and second, a bank number for every reference that can be proven to access a single, known bank for that data distribution. Finally, the thesis shows why non-disambiguated accesses are sometimes desirable. Dependences between disambiguated and non-disambiguated accesses are enforced through explicit synchronization and software serial ordering. The MIT Raw machine is an example of a software-exposed architecture. Raw exposes its ILP, memory and communication mechanisms. The Maps system has been implemented in the Raw compiler. Results on Raw using sequential codes demonstrate that using bank disambiguation in addition to ILP improves performance by a factor of 3 to 5 over using ILP alone.
机译:微处理器必须同时利用指令级并行性(ILP)和内存并行性才能实现高性能。适用于ILP的精密技术增强了现代微处理器在可用时利用ILP的能力。不幸的是,微处理器中存储器并行性的改进落后了。本文解释了为什么在微处理器中难以利用内存并行性,并主张将存储库公开的体系结构作为利用更多内存并行性的有效方法。银行公开的体系结构是一种软件公开的体系结构:其中硬件的低级细节对软件可见。在存储体公开的体系结构中,软件可以看到存储体,从而使编译器除ILP之外还可以利用高度的存储器并行性。通用处理器和嵌入式芯片(例如用于数字信号处理的芯片)都可以使用暴露于银行的架构。本文介绍了Maps,这是一种适用于银行公开架构的编译器技术。 Maps解决了库消除歧义的问题,即,如何在多个库之间的顺序程序中分配数据以最好地利用内存并行性,同时又保留了消除每个数据引用对特定库的歧义的能力。提出了两种消除银行歧义的方法:等价类统一和模展开。将顺序程序作为输入,存储区消歧方法会产生两个输出:第一,每个程序对象在存储区之间的分配;其次,每个参考的库号,可以证明可访问该数据分发的单个已知库。最后,论文表明了为什么有时需要无歧义的访问。通过明确的同步和软件序列排序,可以消除歧义访问和非歧义访问之间的依赖性。 MIT Raw机器是软件公开体系结构的一个示例。 Raw公开了其ILP,内存和通信机制。 Maps系统已在Raw编译器中实现。使用顺序代码在Raw上进行的结果表明,与仅使用ILP相比,除ILP之外,使用存储库消歧还​​可以将性能提高3到5倍。

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