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Design considerations for a digital audio Class D output stage with emphasis on hearing aid application

机译:数字音频D类输出级的设计考虑因素,重点是助听器应用

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摘要

This work deals with power optimization of the audio signal processing back end (the interpolation filter, the ΣΔ modulator and the Class D power amplifier) as a whole. Understanding of the design parameter tradeoffs is used to derive the specifications for the back end and to understand the state-of-the-art. A figure-of-merit which allows judging the power consumption of the digital part of the back end early in the design process is proposed. The insight into the tradeoffs involved is subsequently used to optimize the interpolation filter and the system-level parameters of the ΣΔ modualtor so that the switching frequency of the Class D power amplifier – the main power consumer in the back end - is minimized.• In the multistage interpolation filter the first stage is implemented as a half-band IIR filter consisting of two parallel all-pass cells. A novel approach that does not require any rigorous numerical techniques is proposed to quantize the filter coefficients. Together with the simple all-pass cells the resulting filter has very low hardware / power demands compared to the state-of-the-art.• The switching frequency of the Class D power amplifier is reduced at the cost of the increase of the maximum clock frequency in the digital part of the back end. This approach moves the burden from the Class D power amplifier to the digital part, which easily scales with the IC technologies of today - optimized for digital design.• Judging by the figure-of-merit five design iterations are performed that lower the power consumption of the interpolation filter combined with the ΣΔ modulator by 82% and the switching frequency of the Class D power amplifier by 94% compared to the initial design.• The result is the digital part of the back end optimized with respect to power, which provides audio performance comparable to the state-of-the-art. This is combined with the lowest switching frequency of the Class D power amplifier reported in literature for the ΣΔ modulator-based digital back end.Future work for the digital ΣΔ modulator and the power amplifier with feedback is proposed.
机译:这项工作总体上涉及音频信号处理后端(插值滤波器,ΣΔ调制器和D类功率放大器)的功率优化。了解设计参数需要权衡利弊,以得出后端的规格并了解最新技术。提出了一种品质因数,该品质因数可在设计过程中尽早判断后端数字部分的功耗。随后,可以利用对折衷的见解来优化插值滤波器和ΣΔ调制器的系统级参数,以使D类功率放大器(后端的主要功耗)的开关频率最小化。多级插值滤波器第一级实现为由两个并行全通单元组成的半带IIR滤波器。提出了一种不需要任何严格数值技术的新颖方法来量化滤波器系数。与简单的全通单元一起使用,与现有技术相比,最​​终的滤波器对硬件/功率的需求非常低。•D类功率放大器的开关频率降低了,但代价是增加了最大值后端数字部分的时钟频率。这种方法将负担从D类功率放大器转移到了数字部分,可以轻松地通过当今的IC技术进行扩展-已针对数字设计进行了优化。•从品质因数判断,执行了五次设计迭代以降低功耗与初始设计相比,与ΣΔ调制器组合的插值滤波器的频率降低了82%,D类功率放大器的开关频率降低了94%。•结果是针对功率进行了优化的后端数字部分,从而提供了音频性能可与最新技术媲美。结合文献中报道的基于ΣΔ调制器的数字后端的D类功率放大器的最低开关频率,提出了数字ΣΔ调制器和带反馈功率放大器的未来工作。

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