This work presents a mathematical analysis of HP's memristor models, a skeleton integrator circuit which utilises a memristor, a CMOS-based weak inversion memristor dynamics emulator and a CMOS implementation of a neural network which employs memristors. The implications of the nonlinear dynamics of the memristor and its property of integrating its input are studied. By using an adjustable piecewise input signal, memristance is studied for various excitation signals for current driven and voltage driven memristor models. The importance of the timing, the amplitude and DC offset of the input signal and the resulting mean value with regards to how memristance variation is affected is investigated. A symbolic analysis of a simple memristor-capacitor circuit is carried out inspired by the simplest neuron model of a resistor-capacitor circuit.udududHaving understood the dynamics exhibited by HP's memristor, the integration property of the device is exploited to attain a memristor-based, low power, capacitor-less, CMOS integrator circuit operating in weak inversion. Simulation results showing frequency and transient responses of the circuit are presented. The implications of varying memristor characteristics upon the operation of the integrator are investigated. Inspired by the natural nonlinear dynamics exhibited by CMOS devices operating in weak inversion, a compact, nanopower memristor dynamics integrator is presented. The memristive output of this emulator can be related to a charge-driven prototype memristor with a flux exponentially related to its charge. The memristor is also introduced to a CMOS implementation of a neural network known as a central pattern generator. The effect of including memristors in different configurations upon the nonlinear biological dynamics exhibited by this circuit is observed. The variation in the oscillation amplitude, rhythm and the added stability due to the memristors are reported. This work is a study of memristive dynamics and proposes various applications of this component which governs integration capabilities and can offer power efficient operation and low area consumption in analogue circuits.
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机译:这项工作提出了对惠普忆阻器模型的数学分析,利用忆阻器的骨架积分器电路,基于CMOS的弱反转忆阻器动态仿真器以及采用忆阻器的神经网络的CMOS实现。研究了忆阻器的非线性动力学及其对输入进行积分的性质。通过使用可调分段输入信号,针对电流驱动和电压驱动忆阻器模型研究了各种激励信号的忆阻。研究了时序,输入信号的幅度和DC偏移以及产生的平均值对忆阻变化的影响的重要性。在电阻电容电路的最简单神经元模型的启发下,对简单的忆阻电容电路进行了符号分析。 ud ud ud了解了惠普忆阻器的动态特性后,该器件的集成特性得以实现一种基于忆阻器的低功耗,无电容,CMOS积分器电路,以弱反相工作。仿真结果显示了电路的频率和瞬态响应。考察了忆阻器特性变化对积分器工作的影响。受到以弱反转运行的CMOS器件所展现的自然非线性动力学的启发,提出了一种紧凑的纳瓦级忆阻器动力学积分器。该仿真器的忆阻输出可以与电荷驱动的原型忆阻器相关,其通量与其电荷呈指数关系。忆阻器也被引入到称为中央模式生成器的神经网络的CMOS实现中。观察到包括不同配置的忆阻器对该电路表现出的非线性生物动力学的影响。记录了由于忆阻器引起的振荡幅度,节奏变化和增加的稳定性。这项工作是对忆阻动力学的研究,并提出了该组件的各种应用程序,这些应用程序控制着集成能力,并可以在模拟电路中提供高能效操作和低面积消耗。
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