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Development of SiC heterojunction power devices

机译:siC异质结功率器件的研制

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摘要

Silicon carbide (SiC), with its wide bandgap, high thermal conductivity and natural oxide is a substrate that has given rise to a new generation of power devices than can operate at high temperature, high power and high frequency, though the material is not without its problems. SiC "heterojunction devices" are layers of germanium (Ge) or silicon (Si) that are deposited via molecular beam epitaxy (MBE) or wafer bonded onto the SiC surface. These narrow bandgap thin films can provide a high mobility channel region overcoming SiC's crippling channel mobility, which is most often made worse by a high density of interface states. Concentrating predominantly on Ge/SiC heterojunctions, this thesis characterises the physical and electrical nature of these structures, investigating the rectifying properties of the heterojunction interface and the ability of these layers to support a depletion region. A physical analysis of the layers revealed that the Ge formed in an unexpectedly uniform fashion, given the large lattice mismatch involved. At a deposition temperature of 500oC the Ge initially clumped into wide, shallow islands before merging, forming at best a 300 nm polycrystalline layer with a surface roughness of only 6 nm. This was in contrast to MBE deposited Si/SiC layers that formed tall islands that at 1 μm thick, still had not merged. After being formed into Ge/SiC heterojunction diodes they were electrically characterised. The layers displayed near ideal (η = 1:05) turn-on characteristics, low turn-on voltage (approximately 0.3 V less than Ni/SiC SBDs), reasonable on-resistance (12 m­Ωcm2) and minimal leakage current. The devices were shown to suffer severe Fermi level pinning that defined the way the materials' bands aligned. This occurred as a result of an inhomogeneous interface that also caused fluctuations in the size of the Schottky barrier height across the interface. New characterisation techniques relating to these phenomena were applied to a heterojunction for the first time. MBE formed Ge/SiC layers and wafer bonded Si/SiC layers were formed into MOS capacitors through the deposition of the high-K dielectric hafnium oxide (HfO2). The increased conduction band offset between oxide and narrow bandgap semiconductor suppressed leakage problems often seen in HfO2/SiC structures. Capacitance-voltage results showed that they could both support a depletion region, though the best results came from the MBE Ge/SiC diodes. Current-voltage results showed that the more uniform Si/SiC devices could block 3.5 MV/cm.
机译:具有宽禁带,高导热性和天然氧化物的碳化硅(SiC)成为了新一代功率器件的基底,尽管该材料并非没有,但它们可以在高温,高功率和高频下工作它的问题。 SiC“异质结器件”是锗(Ge)或硅(Si)层,通过分子束外延(MBE)或晶圆结合在SiC表面上而沉积。这些窄带隙薄膜可以提供高迁移率的沟道区域,从而克服SiC的脆性沟道迁移率,而这通常是由于界面态密度高而变得更糟。本论文主要集中在Ge / SiC异质结上,表征了这些结构的物理和电学性质,研究了异质结界面的整流特性以及这些层支持耗尽区的能力。对层的物理分析表明,考虑到所涉及的大晶格失配,Ge以出乎意料的均匀方式形成。在沉积温度为500oC时,Ge最初会聚集成宽的浅岛,然后合并,最多形成300 nm的多晶层,其表面粗糙度仅为6 nm。这与MBE沉积的Si / SiC层形成了高岛,而1μm厚的岛仍未合并,形成了鲜明的对比。在形成Ge / SiC异质结二极管后,对其进行了电学表征。这些层显示出接近理想的开启特性(η= 1:05),低的开启电压(比Ni / SiC SBD大约低0.3 V),合理的导通电阻(12 m­Ωcm2)和最小的泄漏电流。这些设备受到严重的费米能级钉扎,这确定了材料条带对齐的方式。这是由于界面不均匀而导致的,该界面也引起了跨越界面的肖特基势垒高度尺寸的波动。与这些现象有关的新的表征技术首次应用于异质结。 MBE形成的Ge / SiC层和晶片键合的Si / SiC层通过高K电介质氧化oxide(HfO2)的沉积形成为MOS电容器。氧化物和窄带隙半导体之间导通带偏移的增加抑制了HfO2 / SiC结构中经常出现的泄漏问题。电容电压结果表明它们都可以支持耗尽区,尽管最好的结果来自MBE Ge / SiC二极管。电流-电压结果表明,更均匀的Si / SiC器件可以阻挡3.5 MV / cm。

著录项

  • 作者

    Gammon P M;

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  • 年度 2011
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  • 原文格式 PDF
  • 正文语种 English
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