Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital Converters

摘要

Analog-to-digital converters are critically important in electronic systems. Thedifficulty in meeting high performance parameters increases as integrated circuit designprocess technologies advance into the deep nanometer region. Sigma-delta analog-todigitalconverters are an attractive option to fulfill many data converter requirements.These data converters offer high performance while relaxing requirements on the precisionof components within an integrated circuit. Despite this, the active integrators found withinsigma-delta analog-to-digital converters present two main challenges. These challenges arethe power consumption of the active amplifier and achieving gain-bandwidth necessary forsigma-delta data converters in deep nanometer process technologies. Both of thesechallenges can be resolved through the replacement of active integrators with passiveintegrators at the expense of resolution.Three passive sigma-delta topologies were examined and characterized in detail.Two of these topologies were first-order and second-order noise shaping topologies. A newpassive topology was developed which was determined to be optimal in resolutioncompared to the two traditional designs. This topology exhibits a first-order signal transferfunction and a second-order noise transfer function. A method for increasing resolution ofpassive sigma-delta data converters despite inherent performance constraints wasdeveloped.Three example circuits were designed, fabricated and tested using OnSemiconductor’s C5 500 nanometer CMOS process. These designs were optimized for lowpower and utilized memory sense amplifiers as quantizing elements. The first circuit, usingpassive lumped on-chip elements for the noise shaping network achieved a powerconsumption of 100 micro-watts and an effective resolution of 8-bits. The second circuitreplaced the lumped components with switched-capacitor elements and achieved a powerconsumption of 6.75 micro-watts and an effective resolution of 9.3 bits. The third circuitwas designed as a case study for the application of the proposed topology to “K-delta-1-sigma” modulators. This circuit achieved a power consumption of 10 milli-watts and aneffective resolution of 8.5 bits.