Implementation of the AES-128 on Virtex-5 FPGAs

摘要

This paper presents an updated implementation of the advanced encryption standard (AES) on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in these reconfigurable hardware devices results in significant improvement of the design efficiency. In particular, a single substitution box of the AES can fit in 8 FPGA slices. We combine these technological changes with a sound intertwining of the round and key round functionalities in order to produce encryption and decryption architectures that perfectly fit with the digital cinema initiative specifications. More generally, our implementations are convenient for any application requiring Gbps-range throughput.