Design and optimisation of system architecture and communications methods for visual prostheses

摘要

Biomedical engineering combines myriad engineering disciplines, developing and applying novel technologies and approaches to improve quality of life. Visual prostheses are one example, aiming to provide artificial vision to those with profound visual impairment. This is achieved through elicitation of spots of light, a phenomenon known as phosphenes, the feasibility of which has been clearly demonstrated in the past.Visual prostheses with a high number of electrodes are now the subject of intensive research, with recent clinical trials reinforcing the efficacy of such devices. Several architectures have been proposed to address numerous challenges associated with high resolution devices, with the prominent restrictions being on the volume and power available.A multi-implant architecture is a solution to address the aforementioned challenges, however now the difficulties lie in ensuring safety of the inter-implant interface by addressing the associated risks, often neglected in the past. Such an architecture also requires improvements on the communications methods between the external device and the implant to meet high data rate and the low power requirements of a high resolution device.In the first part of this thesis, a new wireless transceiver suitable for multi-coil configuration is presented. The forward link, from the external device to the implant, incorporates a displacement variation tolerant frequency shift keying demodulator, with the backward link realised using an active on-off keying transmitter. To achieve low power requirements, a new semi-static threshold-triggered delay element has been investigated and fabricated using a 0.35 µm HVCMOS technology, exhibiting superior performance over other conventional delay elements.The second part of this thesis addresses the path of investigation towards a multi-implant architecture based 98 channel neurostimulator with an inter-implant interface consisting only of two wires, carrying both power and semi-duplex data. The interface is AC-coupled to both prevent high levels of DC current in the presence of insulation failures and to maintain a charge balanced interface. This interface is monitored for leakage currents within the stimulator itself. The stimulator is fabricated using a 0.35 µm HV CMOS technology and occupies 4.9 x 4.9 mm2 without the need of any external discrete components, making it suitable for chip-scale packaging.