CMOS technology scaling, the process of shrinking transistor dimensions basedon Moore's law, has been the thrust behind increasingly powerful integrated circuitsfor over half a century. As dimensions are scaled to few tens of nanometers, processand environmental variations can significantly alter transistor characteristics, thusdegrading reliability and reducing performance gains in CMOS designs with technologyscaling. Although design solutions proposed in recent years to improve reliabilityof CMOS designs are power-efficient, the performance penalty associated with thesesolutions further reduces performance gains with technology scaling, and hence thesesolutions are not well-suited for high-performance designs.This thesis proposes approximate logic circuits as a new logic synthesis paradigmfor reliable, high-performance computing systems. Given a specification, an approximatelogic circuit is functionally equivalent to the given specification for a "significant"portion of the input space, but has a smaller delay and power as compared to acircuit implementation of the original specification. This contributions of this thesisinclude (i) a general theory of approximation and efficient algorithms for automatedsynthesis of approximations for unrestricted random logic circuits, (ii) logic design solutionsbased on approximate circuits to improve reliability of designs with negligibleperformance penalty, and (iii) efficient decomposition algorithms based on approxiiiimate circuits to improve performance of designs during logic synthesis. This thesisconcludes with other potential applications of approximate circuits and identifies. openproblems in logic decomposition and approximate circuit synthesis.
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