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Real Time 3-D Graphics Processing Hardware Design using Field-Programmable Gate Arrays.

机译:使用现场可编程门阵列的实时3-D图形处理硬件设计。

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摘要

Three dimensional graphics processing requires many complex algebraic and matrix based operations to be performed in real-time. In early stages of graphics processing, such tasks were delegated to a Central Processing Unit (CPU). Over time as more complex graphics rendering was demanded, CPU solutions became inadequate. To meet this demand, custom hardware solutions that take advantage of pipelining and massive parallelism become more preferable to CPU software based solutions. This fact has lead to the many custom hardware solutions that are available today. Since real time graphics processing requires extreme high performance, hardware solutions using Application Specific Integrated Circuits (ASICs) are the standard within the industry. While ASICs are a more than adequate solution for implementing high performance custom hardware, the design, implementation and testing of ASIC based designs are becoming cost prohibitive due to the massive up front verification effort needed as well as the cost of fixing design defects.Field Programmable Gate Arrays (FPGAs) provide an alternative to the ASIC design flow. More importantly, in recent years FPGA technology have begun to improve in performance to the point where ASIC and FPGA performance has become comparable. In addition, FPGAs address many of the issues of the ASIC design flow. The ability to reconfigure FPGAs reduces the upfront verification effort and allows design defects to be fixed easily. This thesis demonstrates that a 3-D graphics processor implementation on and FPGA is feasible by implementing both a two dimensional and three dimensional graphics processor prototype. By using a Xilinx Virtex 5 ML506 FPGA development kit a fully functional wireframe graphics rendering engine is implemented using VHDL and Xilinx's development tools. A VHDL testbench was designed to verify that the graphics engine works functionally. This is followed by synthesizing the design and real hardware and developing test applications to verify functionality and performance of the design. This thesis provides the ground work for push forward the use of FPGA technology in graphics processing applications.
机译:三维图形处理需要实时执行许多复杂的基于代数和矩阵的运算。在图形处理的早期阶段,此类任务被委派给中央处理单元(CPU)。随着时间的流逝,要求更复杂的图形渲染,CPU解决方案变得不足。为了满足这一需求,利用流水线和大规模并行性的定制硬件解决方案变得比基于CPU软件的解决方案更为可取。这一事实导致了当今可用的许多定制硬件解决方案。由于实时图形处理需要极高的性能,因此使用专用集成电路(ASIC)的硬件解决方案是业界的标准。尽管ASIC是实现高性能定制硬件的合适解决方案,但由于需要大量的前期验证工作以及解决设计缺陷的成本,基于ASIC的设计的设计,实施和测试变得成本过高。门阵列(FPGA)提供了ASIC设计流程的替代方案。更重要的是,近年来,FPGA技术已开始将性能提高到ASIC和FPGA性能可比的地步。此外,FPGA解决了ASIC设计流程中的许多问题。重新配置FPGA的能力减少了前期验证工作,并使设计缺陷易于修复。本文证明,通过同时实现二维和三维图形处理器原型,在FPGA上实现3-D图形处理器是可行的。通过使用Xilinx Virtex 5 ML506 FPGA开发套件,可以使用VHDL和Xilinx的开发工具来实现功能齐全的线框图形渲染引擎。 VHDL测试平台旨在验证图形引擎是否正常运行。接下来是综合设计和实际硬件,并开发测试应用程序以验证设计的功能和性能。本文为推动FPGA技术在图形处理应用中的应用奠定了基础。

著录项

  • 作者

    Warner James Ryan;

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  • 年度 2009
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  • 原文格式 PDF
  • 正文语种 en
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