An architecture for multi-layer feed-forward neural networks.

摘要

Feed-forward neural networks can perform classifications and generalizations that are difficult to achieve with any other known method, and their performance matches or surpasses that of the conventional methods. To utilize the potential of these networks to the fullest, however, an efficient hardware implementation is needed. In this thesis, an architecture for efficient implementation of food-forward multi-layer neural networks is introduced. The interconnection congestion problem is addressed by a multiplexing scheme, which reduces the number of physical interconnections without any loss of generality. The building blocks are mostly in current mode analog CMOS, and the connection strengths of the network are stored in a digital memory. Also included in this thesis is a performance analysis of the architecture and a study of the effects of quantization and truncation of connection strengths on network performance.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses u26 Major Papers - Basement, West Bldg. / Call Number: Thesis1991 .N687. Source: Masters Abstracts International, Volume: 31-01, page: 0398. Co-Supervisors: M. Ahmadi; M. Shridhar. Thesis (M.A.Sc.)--University of Windsor (Canada), 1991.