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Realization of III-V semiconductor nano structures towards more efficient (otpo-) electronic devices

机译:实现III-V半导体纳米结构以实现更高效的(OTPO-)电子设备

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摘要

Solid state electronics and their application in personal computers, smartphones, digital cameras and entertainment devices (to name a few) have gained such a rapid progress that it’s already barely imaginable how our future technological environment will evolve in the next few years. In parallel, however, concerns about excessive use of the world’s limited natural energy resources has led to a rethinking with respect to the design and production of future electronics. One of the most promising solutions to further improve the efficiency of electronics is the combination of the well established silicon technology with III-V semiconductor nano structures which have been extensively investigated in various fields for the last few decades. InAs nano structures, in particular, are intrinsically conductive due to their characteristic conduction band profile, caused by surface states. The materials high bulk carrier mobility gives rise to expect a significant boost in efficiency of electronic devices that employ InAs nano structures. In this work, three different aspects of device improvement are addressed: the exchange of channel material in traditional CMOS, the development of new nanostructure based concepts and the use of direct band gap properties for more cost-effective sensing devices. The established SA MOVPE of III-V nano structures on III-V substrates serves as a starting point. Systematic experiments are conducted in order to address several significant questions regarding the suitability of III-V nano structures as building blocks for future electronic devices. It is found that a large variety of free-standing InAs nanowires with different properties can be produced in an ordered and controlled fashion. The results show that uniform InAs nanowires with a high aspect ratio can be produced selectively on GaAs(111)B and GaAs(110) oriented surfaces, the latter being also a natural cleaved edge direction of industrially used Si(001) substrates. In addition, very thin InAs nanowires with diameters down to 20 nm are obtained as a side effect on non-structured cleaved-edge sidewalls of GaA (001). N-type doping with disilane is found to have a general impact on the nanowire morphology, resulting in a reduced height vs. diameter aspect ratio with an increased amount of doping applied during deposition. It is observed that all wires exhibit an intrinsic conductivity with an ohmic behavior which is further increased after doping. Also, the nanowire diameter is found to be a potential parameter to tune their electronic properties. A series of experiments with different growth parameters and the successive characterization of the nanowires‘ crystal structure reveal that different group-V partial pressures affect the formation of stacking faults and the crystal‘s wurtzite to zinc blende ratio. A significant step to combine the gained knowledge on controlled bottom-up InAs nanowire fabrication and benefits of SA MOVPE in N2 ambient with current silicon technology is the transition of InAs growth to silicon substrates. The technique of flow modulated epitaxy is adopted from MOVPE growth in hydrogen ambient and adapted and optimized for growth in N2 in order overcome the lack of polarity on silicon. As a result, InAs nanowire growth on Si(111) is carried out with a high yield of vertical wires. After the investigation of free standing InAs nanowires mainly for concepts exceeding CMOS, a methodology for the deposition of lateral InAs nano structures on silicon by SA MOVPE was presented, aimed towards the exchange of channel material in current planar electronic devices. Growth parameters adopted from GaAs/InAs core-shell nanowire growth are applied to a variety of differently oriented and patterned substrates. The obtained lateral structures are characterized with respect to morphology, crystal structure and electronic properties. High crystallinity and conductivity are found and discussed in comparison to the results obtained from vertical nanowires. Finally, quantum cascade structures based on ternary III-V semiconductors with high indium content are investigated with respect to single mode emission for gas sensing applications. It is found that curved laser waveguides are capable of single mode emission which is explained by the interaction of coupled cavities, resulting in strong side mode suppression. The monolithic approach without need for complicated sample processing has tremendous potential for the fabrication of cost effective and portable gas sensing devices.
机译:固态电子及其在个人计算机,智能手机,数码相机和娱乐设备(仅举几例)中的应用取得了如此迅速的进步,以至于我们未来的技术环境在未来几年中将如何发展已经是不可想象的了。但是,与此同时,由于担心过度使用世界上有限的自然能源,导致人们对未来电子产品的设计和生产进行了重新思考。进一步提高电子效率的最有前途的解决方案之一是将成熟的硅技术与III-V半导体纳米结构相结合,这在最近几十年中已在各个领域进行了广泛研究。由于表面态导致的InAs纳米结构的特征导带分布,InAs纳米结构尤其具有固有的导电性。材料的高整体载流子迁移率引起人们对采用InAs纳米结构的电子设备效率的显着提高。在这项工作中,解决了设备改进的三个不同方面:传统CMOS中通道材料的交换,基于纳米结构的新概念的发展以及对更具成本效益的传感设备使用直接带隙特性。在III-V衬底上建立的III-V纳米结构的SA MOVPE作为起点。为了解决有关III-V纳米结构作为未来电子设备构建基块的适用性的几个重要问题,进行了系统的实验。发现可以以有序和受控的方式生产具有不同特性的各种独立的InAs纳米线。结果表明,可以有选择地在GaAs(111)B和GaAs(110)取向的表面上生产出具有高深宽比的均匀InAs纳米线,后者也是工业上使用的Si(001)衬底的自然分裂边缘方向。另外,获得了直径低至20 nm的非常细的InAs纳米线,作为对GaA(001)的非结构化裂边侧壁的副作用。发现用乙硅烷进行的N型掺杂通常会对纳米线的形貌产生影响,从而导致高度与直径的长径比减小,同时沉积过程中掺杂的数量增加。可以观察到,所有导线都表现出具有欧姆特性的固有导电性,该特性在掺杂后会进一步增加。同样,发现纳米线的直径是调节其电子性能的潜在参数。一系列具有不同生长参数的实验以及对纳米线晶体结构的连续表征表明,不同的V组分压会影响堆垛层错的形成以及晶体纤锌矿与锌的混合比。将获得的有关自底向上的InAs纳米线可控制造方面的知识与SA MOVPE在N2环境中的优势与当前的硅技术相结合的重要一步是InAs生长向硅衬底的转变。流动调制外延技术从氢环境中的MOVPE生长中采用,并针对N2的生长进行了调整和优化,以克服硅上缺乏极性的问题。结果,以高产率的垂直线在Si(111)上进行InAs纳米线生长。在主要针对超过CMOS的概念研究了独立式InAs纳米线之后,提出了一种通过SA MOVPE在硅上沉积横向InAs纳米结构的方法,旨在交换当前平面电子设备中的沟道材料。从GaAs / InAs核壳纳米线生长中采用的生长参数被应用于各种不同取向和图案化的衬底。所获得的横向结构在形态,晶体结构和电子性能方面得到表征。与从垂直纳米线获得的结果相比,发现并讨论了高结晶度和导电性。最后,针对气体传感应用的单模发射,研究了基于具有高铟含量的三元III-V半导体的量子级联结构。发现弯曲的激光波导能够发出单模发射,这可以通过耦合腔的相互作用来解释,从而导致强的侧模抑制。无需复杂样品处理的整体方法对于制造经济高效的便携式气体传感设备具有巨大的潜力。

著录项

  • 作者

    Sladek Kamil Przemyslaw;

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  • 年度 2013
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  • 原文格式 PDF
  • 正文语种 eng
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