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Current transport behaviour of Au/n-GaAs Schottky diodes grown on Ge substrate with different epitaxial layer thickness over a wide temperature range

机译:在宽温度范围内生长在具有不同外延层厚度的Ge衬底上的Au / n-GaAs肖特基二极管的电流传输行为

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摘要

The work presents temperature dependent forward and reverse current-voltage (I-V) analyses of n-GaAs/Au Schottky Diodes grown on n+ Ge substrate with different epitaxial layer thicknesses. While some of the Schottky diodes follow TED mechanism, others exceed significantly from this theory due to existence of patches of reduced barrier height embedded in the Schottky interface. The zero bias barrier heights (φbo) increase (0.649 to 0.809 eV) while the ideality factors (η) decrease (1.514 to 1.052) with increase in epitaxial layer thickness (1-4 μm), thus, indicating similar behaviour to that observed for the I-V characteristics of the undertaken Schottky diodes with decreasing temperature. It all indicated the existence of barrier inhomogenities over the M-S interface. The breakdown behaviour analysis of these diodes showed some interesting results; the breakdown voltage (VBR) decreases with temperature and shows ‘Defect Assisted Tunneling’ phenomenon through surface or defect states in the 1 μm thick epitaxial layer Schottky diode while VBR increases with temperature in 3 μm and 4 μm thick epitaxial layer Schottky diodes which demonstrate ‘Avalanche Multiplication’ mechanism responsible for junction breakdown. The reverse breakdown voltage is also seen to increase (2.7-5.9 Volts) with the increase in epitaxial layer thickness of the diodes. The undertaken diodes have been observed to follow TFE mechanism at low temperatures (below 200 K) in which the tunneling current component increases with epitaxial layer thickness which has been ascribed as an impact of GaAs/Ge hetero-interface over the Au/n-GaAs Schottky barrier.When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/27885
机译:这项工作提出了生长在具有不同外延层厚度的n + Ge衬底上的n-GaAs / Au肖特基二极管的温度相关正向和反向电流-电压(I-V)分析。尽管某些肖特基二极管遵循TED机制,但由于嵌入在肖特基界面中的势垒高度减小的贴片的存在,其他肖特基二极管大大超出了该理论。零偏压势垒高度(φbo)随着外延层厚度(1-4μm)的增加而增加(0.649至0.809 eV),而理想因子(η)则减少(1.514至1.052),因此,其行为与观察到的相似。随温度降低,肖特基二极管的IV特性。所有这些都表明在M-S界面上存在势垒不均匀性。这些二极管的击穿行为分析显示了一些有趣的结果。击穿电压(VBR)随温度降低,并在1μm厚的外延层肖特基二极管中通过表面或缺陷状态表现出“缺陷辅助隧穿”现象,而VBR在3μm和4μm厚的外延层肖特基二极管中随温度升高而增加。雪崩倍增机制负责结击穿。反向击穿电压也随着二极管外延层厚度的增加而增加(2.7-5.9伏)。已经观察到,所采用的二极管在低温(低于200 K)下遵循TFE机理,其中隧道电流分量随外延层厚度的增加而增加,这归因于GaAs / Ge异质界面对Au / n-GaAs的影响肖特基势垒。在引用文档时,请使用以下链接http://essuir.sumdu.edu.ua/handle/123456789/27885

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