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Noise analysis for switched-capacitor circuitry

机译:开关电容器电路的噪声分析

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摘要

Track and hold circuits play a key role in mixed-signal, analog to digital interfaces. They are often used as part of the analog to digital conversion (ADC) process whereby a time-varying analog signal is sampled at the transition of a clock signal and subsequently held for a part of the conversion process. This approach is used, in part, because the remainder of the ADC conversion process is adversely affected if the input signal varies during the conversion.;Noise, and in particular thermal noise, is recognized as a major bottleneck limiting the performance of switched-capacitor circuits and it is essential that all of the major contributors to noise are appropriately considered when designing any switched-capacitor circuit. Invariably, switched-capacitor (SC) circuit designers only discuss noise generated in the track mode when reporting noise performance and correspondingly ignore noise generated in the hold mode. In particular, most authors simply use the well-known expression kT/C to represent the variance of sampled thermal noise present on a sampling capacitor [16]-[19]. The spectrum of the continuous-time sample and hold noise has been discussed as the switches capacitor circuitry field evolved [1]-[3] but the early authors didn\u27t discuss the relationship between the spectrum of the sample and hold noise and the sampled noise characterized with the kT/C expression. More important, noise present during the hold mode which affects subsequent sampling has not been discussed in the literature. In the thesis, the continuous noise which is generated during the second phase of a SC circuit will be compared to the S/H noise.;In chapter two of this thesis, a numerical comparison between the RMS value of the continuous-time S/H noise and the sampled kT/C noise is presented. In chapter three, thermal noise present during the hold mode for two switched-capacitor circuits which are often used in analog to digital converters are investigated and compared with the standard sampled noise expression. In chapter four, it is shown that when these switched-capacitor circuits are used in an analog to digital converter with low speed and small resolution, the continuous-time hold noise can be justifiably neglected but when the sample frequency and resolution get higher, the noise that is generated in the hold phase is not negligible and can cause significant performance degradation of the system.
机译:跟踪和保持电路在混合信号,模数接口中起着关键作用。它们通常用作模数转换(ADC)过程的一部分,通过该过程,时变模拟信号在时钟信号的跃迁处进行采样,并随后保留为转换过程的一部分。之所以使用这种方法,部分原因是如果在转换过程中输入信号发生变化,则会对ADC转换过程的其余部分产生不利影响;噪声(尤其是热噪声)被认为是限制开关电容器性能的主要瓶颈在设计任何开关电容器电路时,必须适当考虑所有主要的噪声源。不变地,开关电容器(SC)电路设计人员仅在报告噪声性能时才讨论在跟踪模式下产生的噪声,并相应地忽略在保持模式下产生的噪声。特别是,大多数作者只是简单地使用众所周知的表达式kT / C来表示采样电容器[16]-[19]上存在的采样热噪声的方差。随着开关电容器电路领域的发展,已经讨论了连续时间采样和保持噪声的频谱[1]-[3],但是早期的作者没有讨论采样和保持噪声的频谱与采样噪声之间的关系。噪声以kT / C表达式表示。更重要的是,在保持模式期间存在的会影响后续采样的噪声尚未在文献中讨论。本文将在SC电路第二阶段产生的连续噪声与S / H噪声进行比较。在本文的第二章中,对连续时间S / RMS值进行数值比较。给出了H噪声和采样的kT / C噪声。在第三章中,研究了在两个模数转换器中常用的两个开关电容器电路在保持模式期间存在的热噪声,并将其与标准采样噪声表达式进行了比较。第四章表明,当将这些开关电容器电路用于低速,低分辨率的模数转换器时,可以合理地忽略连续时间保持噪声,但是当采样频率和分辨率变高时,在保持阶段产生的噪声是不可忽略的,并且可能导致系统的显着性能下降。

著录项

  • 作者

    Gai, Yingkun;

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  • 年度 2008
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  • 原文格式 PDF
  • 正文语种 en
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