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Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)

机译:子分辨率定向自组装辅助功能(SDRAF)布局的设计策略

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摘要

In the pursuit of alternatives to optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. DSA uses small topographical templates to contain the block copolymer and create small clusters of holes useful for patterning vias [1]. However, issues of defectivity have hampered DSA'€™s viability for large-scale patterning. Recent studies have shown polymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures [2]. The inherent density variations in via layouts, though, make regions of overfilled templates nearly inevitable, as templates in less dense regions will contain more polymer. For this reason, we develop a method to integrate sub-DSA resolution assist features (SDRAFs) into DSA template layouts. The SDRAFs divert excess polymer from the overfilled main templates but are themselves too small to form transferrable DSA patterns [2]. Thus, we can populate low-density regions with SDRAFs to make a layout more uniformly dense. To do this, we use SDRAFs with a set of lithography-based design rules dictating the minimum pitch and resist thickness between features (95 nm and 45 nm for 193i, respectively). The SDRAF CD is also chosen to be as large as possible without forming a transferrable DSA pattern, setting it at 40 nm for an L0 = 40 nm polymer and a PS wetting flow. With these rules, we set a flow for the assignment of each SDRAF according to the calculated density of templates in each block. We demonstrate the process on a 2.5 x 2.5 um section from V23 (the via layer connecting metals 2 and 3) of a routed N7 Cortex-M0 processor scaled to a 24 nm via layout grid. We first overlay the template layout with a grid of SDRAFs spaced at 96 nm, allowing the SDRAFs to align with the via grid. We then remove the SDRAFs that violate the minimum resist or pitch rules and assess the density result. This is done by dividing the layout into blocks and calculating the percentage of area occupied by the main and assist templates in the blocks, using prior experimental data for template area [3]. The size of the blocks is set to the length over which the polymer reflows during the thermal anneal [4], assumed here to be about 500 nm. Finally, the SDRAF grid is shifted vertically and horizontally in increments of the via grid (24 nm) to achieve different density results, as each shift causes different SDRAFs to be in violation. We can then choose the shift that minimizes the density variation across the blocks as the final layout. In our test case, we found that the density range of the blocks changed from 2.8-8.6% to 10.9-12.9% post-SDRAF assignment. Here, the polymer film thickness can be adjusted to accommodate the higher overall density and the narrowed density range shows promise to reduce template overfill. Future work will incorporate methods of improving the layout's PV band to create an SDRAF design strategy that is more DSA- and lithography-friendly.[1] H. Yi et al., Adv. Mater 24, 23 (2012). [2] H. Yi et al., Proc. SPIE 9423, 1F (2015). [3] J. Doise et al., J. Vac. Sci. Technol. B 33, 6 (2015). [4] H. Yi et al., Proc. SPIE 9323, 2A (2015).
机译:在寻求光学光刻的替代方法时,嵌段共聚物定向自组装(DSA)已经成为一种低成本,高通量的选择。 DSA使用较小的形貌模板来包含嵌段共聚物,并创建可用于对通孔进行构图的小孔簇[1]。但是,缺陷问题阻碍了DSA进行大规模图案加工的可行性。最近的研究表明,聚合物填充水平是缺陷率的关键因素,因为模板的过度填充会导致DSA结构变形[2]。但是,过孔布局中固有的密度变化使过度填充的模板区域几乎不可避免,因为密度较小的区域中的模板将包含更多的聚合物。因此,我们开发了一种将子DSA解析辅助功能(SDRAF)集成到DSA模板布局中的方法。 SDRAFs从过量填充的主模板中转移了多余的聚合物,但它们本身太小而无法形成可转移的DSA模式[2]。因此,我们可以使用SDRAF填充低密度区域,以使布局更均匀地密集。为此,我们将SDRAF与一组基于光刻的设计规则一起使用,这些规则规定了特征之间的最小间距和抗蚀剂厚度(对于193i,分别为95 nm和45 nm)。还选择了SDRAF CD,使其尽可能大而不形成可转移的DSA图案,对于L0 = 40 nm的聚合物和PS润湿流,将其设置为40 nm。利用这些规则,我们根据每个块中模板的计算密度为每个SDRAF设置了分配流程。我们在通过布局网格缩放到24 nm的路由N7 Cortex-M0处理器的V23(连接金属2和3的通孔层)的2.5 x 2.5 um截面上演示了该过程。我们首先用间隔为96 nm的SDRAF网格覆盖模板布局,从而使SDRAF与过孔网格对齐。然后,我们删除违反最小抗蚀剂或间距规则的SDRAF,并评估密度结果。这是通过将布局划分为多个块,并使用先前的模板面积实验数据[3]来计算主模板和辅助模板在块中所占面积的百分比。块的尺寸设置为在热退火[4]期间聚合物回流的长度,此处假定为约500 nm。最终,随着通孔栅格(24 nm)的增量,将SDRAF栅格垂直和水平移动以实现不同的密度结果,因为每次移动都会导致违反不同的SDRAF。然后,我们可以选择最小化整个块的密度变化的偏移作为最终布局。在我们的测试案例中,我们发现在SDRAF分配后,块的密度范围从2.8-8.6%更改为10.9-12.9%。在此,可以调节聚合物膜的厚度以适应更高的总密度,而狭窄的密度范围则有望减少模板的过度填充。未来的工作将结合改善版图的PV波段的方法,以创建更适合DSA和光刻的SDRAF设计策略。[1] H. Yi et al。,Adv。 Mater 24,23(2012)。 [2] H. Yi等人,美国国家科学院院刊。 SPIE 9423,1F(2015年)。 [3] J. Doise等人,J。Vac。科学技术。 B 33,6(2015)。 [4] H. Yi等人,美国国家科学院学报。 SPIE 9323,2A(2015年)。

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