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Amorf silicium passivatie van dunne heterojunctie achterzijde-gecontacteerde zonnecellen gebonden aan glas

机译:薄异质结背接触太阳能电池与玻璃的非晶硅钝化

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摘要

The climate change observed in the last few years encouraged the development of fossil fuel-free energies, such as photovoltaic (PV) and wind power. However, the diffusion of PV is still limited by the high manufacturing cost and low energy conversion efficiency of PV cells and modules. A strategy to overcome this issue is the fabrication of PV cells using kerf-loss-free wafers that are thinner than the one currently commercialized. In this way, a significant amount of silicon can be saved, decreasing the cost and increasing the efficiency of PV module. The implementation of thin wafers into standard solar cell (and module) manufacturing flow is challenging: thin wafers break more easily than thick wafers, and an increased breakage rate can lower considerably the manufacturing yield. An answer to this problem is provided by the interdigitated interconnected (i2)-module proposed by IMEC. The i2-module is an amorphous/crystalline silicon heterojunction interdigitated back-contact (a-Si:H/c-SI HJ i-BC) module fabricated on thin (40 μm) wafers while bonded to thick (0.7-3 mm) substrates. Specifically, the frontside of the i2-module cell is processed a cell level while the rear side of the wafer is bonded to a silicon substrate by means of a porous silicon layer. The rear side of the i2-module cell is processed at module-level while the wafer is already partially encapsulated in the module glass by means of a silicone-based adhesive. In this way, the thin wafers are mechanically supported during manufacturing: the dependency of the breakage rate on the wafer thickness is eliminated. In the i2-module, the rear side of the cell(s) is processed monolithically on wafers / silicone / glass stacks. The introduction of the glass and silicone at an early stage of the manufacturing process, i.e., prior to rear side processing, imposes constraints to the fabrication flow. In the current thesis, the constraints imposed by the glass and silicone on the process of module-level amorphous silicon (a-Si:H) surface passivation are investigated. The a-Si:H passivation process includes the steps of wet cleaning and a-Si:H Plasma Enhanced Vapor Deposition (PECVD), and the interactions between the glass and silicone with these two steps are investigated separately. Equally, the impact of these interactions on the passivation performances are studied. The presence of glass during wet cleaning does not influence significantly the passivation process. Conversely, the presence of glass during a-Si:H PECVD causes a shift in wafer temperature and electric potential. These two effects can be easily eliminated by modification of the PECVD parameters, obtaining passivation quality similar or, potentially, superior to the one obtained on freestanding wafers. The presence of silicone during the passivation process leads to multiple effects, and these are: 1) silicone-based contamination of the wafer surface during wafer bonding; 2) challenging wet cleaning of the bonded wafer and 3) thermal- and plasma-induced silicone degradations during a-Si:H PECVD. As a result of these effects, the quality of the a-Si:H surface passivation in presence of silicone is compromised. Thus, silicone treatments after bonding and before wet cleaning and a-Si:H PECVD are investigated in order to remove the silicone-based contamination and increase silicone resilience to thermal- and plasma- induced degradation. These treatments are: 1) an additional outgassing of the wafer / silicone / glass stack during the bonding step, whose temperature and time are adjusted to the geometry of the sample and to the subsequent thermal steps; 2) an O2 or Ar plasmas performed in a Reactive Ion Etching (RIE) reactor in order to increase the silicone resilience toward processing and 3) a wet cleaning sequence able to remove the surface contamination of the wafer without attacking the silicone. As a consequence of these treatments, the interactions between the glass, the silicone and the passivation process are eliminated and excellent passivation comparable to the one obtained on freestanding wafers are measured on wafer / silicone / glass stacks (surface recombination velocities below 3 cm/s). Furthermore, an i2-module proof-of-concept (POF) using thick (180 μm) wafers is fabricated and the performances of the freestanding and bonded POFs are compared. Comparable averages Vocs of approximately 660±10 mV are obtained on the freestanding and bonded POFs, confirming at device level the excellent passivation measured on test structures.
机译:过去几年中观察到的气候变化促进了无化石燃料能源的发展,例如光伏(PV)和风力发电。然而,PV的扩散仍然受到PV电池和模块的高制造成本和低能量转换效率的限制。解决这一问题的一种策略是使用比目前商业化的产品更薄的无切口损失的晶圆制造PV电池。这样,可以节省大量的硅,从而降低了成本并提高了PV模块的效率。将薄晶圆实施到标准太阳能电池(和模块)制造流程中具有挑战性:薄晶圆比厚晶圆更容易破裂,并且破损率提高会大大降低制造良率。 IMEC提出的叉指式互连(i2)模块提供了此问题的答案。 i2模块是非晶/结晶硅异质结叉指式背接触(a-Si:H / c-SI HJ i-BC)模块,制造于薄(40μm)晶片上,同时与厚(0.7-3 mm)衬底粘合。具体地,在晶片的背面通过多孔硅层结合到硅衬底的同时,对i2模块单元的正面进行单元级处理。 i2模块电池的背面在模块级别进行了处理,而晶圆已经通过硅酮类粘合剂部分封装在模块玻璃中。以此方式,在制造期间机械地支撑薄晶片:消除了破碎率对晶片厚度的依赖性。在i2模块中,电池的背面在晶圆/硅树脂/玻璃堆叠上进行了整体处理。在制造过程的早期即在背面处理之前引入玻璃和硅树脂,对制造流程施加了约束。在本文中,研究了玻璃和有机硅对模块级非晶硅(a-Si:H)表面钝化过程的约束。 a-Si:H钝化工艺包括湿法清洁和a-Si:H等离子增强气相沉积(PECVD)步骤,并且分别研究了玻璃和有机硅在这两个步骤之间的相互作用。同样,研究了这些相互作用对钝化性能的影响。湿法清洁过程中玻璃的存在不会显着影响钝化过程。相反,在a-Si:H PECVD过程中玻璃的存在会导致晶片温度和电势发生变化。可以通过修改PECVD参数轻松地消除这两种效应,获得的钝化质量与独立晶片上的钝化质量相似,甚至可能更高。钝化过程中硅酮的存在会导致多种效应,这些效应包括:1)硅片键合期间硅片表面对硅片的污染; 2)挑战性的湿法清洗键合晶圆,以及3)a-Si:H PECVD过程中热和等离子体引起的有机硅降解。这些影响的结果是,在存在有机硅的情况下a-Si:H表面钝化的质量受到了损害。因此,研究了粘合后,湿法清洁之前的硅树脂处理以及a-Si:H PECVD,以去除基于硅树脂的污染物并提高硅树脂对热和等离子体诱导降解的弹性。这些处理方法是:1)在键合步骤中,晶圆/硅树脂/玻璃堆叠会产生额外的除气,其温度和时间将根据样品的几何形状以及随后的加热步骤进行调整; 2)在反应离子蚀刻(RIE)反应器中执行O2或Ar等离子体,以提高有机硅对工艺的适应性,以及3)湿法清洁程序,能够去除晶片的表面污染而不会侵蚀有机硅。这些处理的结果是,消除了玻璃,有机硅和钝化过程之间的相互作用,并且在晶片/有机硅/玻璃叠层上测量了与在独立式晶片上获得的钝化相当的钝化效果(表面复合速度低于3 cm / s )。此外,制造了使用厚(180μm)晶片的i2模块概念验证(POF),并比较了独立式POF和粘结式POF的性能。在独立式和键合的POF上获得了约660±10 mV的可比平均Vocs,在器件级别确认了在测试结构上测得的优异钝化性能。

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    Granata Stefano Nicola;

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  • 年度 2014
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