FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems

摘要

This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one basis. With these chips as communication systembuilding blocks, a complex multiprocessor system can be built. Inter-processor communication within the multiprocessor system is accomplishedby passing messages composed of data packets.The resulting chip, called a First-in-first-out Buffering Transceiver(FIBT), provides a full duplex communication channel between any twoprocessors. FIFU queues are provided for buffering data on eachcommunication channel. FIBT accepts data packets from the host processorvia a parallel data bus and serially sends them out to the destined processor.FIBT handshakes with the processor by using asynchronous interrupt signals. Linkage between any two FIBTs is accomplished by using only two wires. Both data bits and handshaking signals are sent by these two lines. Tbe FIBTsystem is neither a synchronous nor an asynchronous one; instead, it is an"one-clock-different-phases" system. A clock signal sets up the frequencyreference; the start and stop bits set up the phase reference.Finally, FIBT is implemented in nMOS technology. The design of thecircuit is discussed in detail. The design is generalized enough so that datapackets of various sizes can be handled. The layout of the chip is coded in anintegrated circuit descriptive language. Any member of the family of chipscan be obtained by changing three basic parameters. Techniques used inverifying the circuit are shown and several observations about VLSI designare offered.