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Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

机译:从DataFlow程序设计域特定的异构体系结构

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摘要

The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures—and, consequently, exploration of the design space—by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately 4 × improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5–13%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.
机译:过去十年来看,使用单个核心推动计算机架构的性能和电源要求在单个芯片上使用数百个核心使用单核来推动计算机架构。为了进一步提高性能和能源效率,我们现在正在看到具有专业和加速核心的异构架构的开发。然而,由于其固有的复杂性,设计这些异构系​​统是一个具有挑战性的任务。我们提出了一种通过将硬件加速器集成到简单的核心来设计基于指令增强来设计域特定异构架构的方法。这些硬件加速器基于其在某个域内的应用程序中的常见使用来确定。目的是通过将许多这些加速核心集成并将其与片上连接来产生异构架构。拟议的方法旨在缓解异构多核架构的设计 - 因此,通过自动化设计步骤来探索设计空间。为了评估我们的方法,我们使用可以从数据流程生成加速核心的工具来增强我们的软件工具链。借助于两种用例评估了新的工具链:雷达信号处理和移动基带处理。我们可以实现性能大约4倍,同时在增强核心上执行完整的应用程序,面积使用的少量影响(2.5-13%)。所生成的加速器具有竞争力,实现了手写实施的90%以上的性能。

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