Efficiency modeling for MHz DCDC converters at 40 V input voltage range

摘要

Size and cost of a switched mode power supply can be reduced by increasingthe switching frequency. This leads especially at a high input voltage to adecreasing efficiency caused by switching losses. Conventional calculationsare not suitable to predict the efficiency as parasitic capacitances have asignificant loss contribution. This paper presents an analytical efficiencymodel which considers parasitic capacitances separately and calculates thepower loss contribution of each capacitance to any resistive element. Theproposed model is utilized for efficiency optimization of converters withswitching frequencies > 10 MHz and input voltages up to 40 V. Forexperimental evaluation a DCDC converter was manufactured in a 180 nm HVBiCMOS technology. The model matches a transistor level simulation andmeasurement results with an accuracy better than 3.5 %. The accuracy of theparasitic capacitances of the high voltage transistor determines the overallaccuracy of the efficiency model. Experimental capacitor measurements can befed into the model. Based on the model, different architectures have beenstudied.