Simulation Based Study of Interleaving in the Cesar-5 Vector Processor

摘要

The key to high bandwidth memory in vector processor systems is memoryinterleaving and efficient interconnection networks. Most interleaving schemes presented during the last two decades are discussed in this thesis. Special attention is paid to Irreducible polynomial (I-poly) interleaving. A new interleaving scheme based on randomized Latin-squares is introduced. Some crossbar networks are analyzed. Emphasis is put on the analysis of the time multiplexed crossbar network chosen for the Cesar-5 vector processor. Some enhancements to this network are also introduced, which improved the throughput. A fetch cache is proposed that improves the performance of repeated accesses to short vectors. An interleaving scheme is proposed for the Cesar-5 vector processor. Finally, simulations of the proposed memory system for the Cesar-5 vector processor are presented.