ULM: A RISC for LISP. System Architecture

摘要

An architecture to execute LISP which combines the benefits of traditional LISPmachine designs and Reduced Instruction Set Computer (RISC) processors is presented. The architecture is scalable because some of the special units can be omitted emulating their functionality by software. The processor features hardware support for a rich set of different data types and a set of highly generic instructions suitable to meet LISP requirements. The proposed processor can be either operated as a LISP coprocessor in a host system or as the CPU of a stand alone computer system. Simulation results show that in combination with a highly optimizing complier the dedicated LISP RISC processor allows an architecture superior to those existing LISP machines and LISP supporting RISC based computers.