Test chips for ASIC qualification. Test chip and fabrication run N06J results. HIRIS data compressor chip. Standard cell and SEU SRAM chip results

摘要

The HIRIS Data Compressor Chip (HDCC) and a JPL standard cell test chip were fabricated at a silicon foundry through the MOSIS prototyping service. The VLSI technology group submitted its full suite of test structures on the run and this report contains the results of the test structure analysis. The SEU/TD radiation monitor was included on the HDCC fabrication run. These chips were packaged, screened, and delivered to the MIT Lincoln Laboratory and will launched be on the MSX (Mid-Course Space Experiment) satellite in 1992.