Parallelization Efficiency of Vectorized Codes: iPSC/860 Case Studies

摘要

This paper describes the manual conversion of several vectorized Fortran algorithms to the iPSC/860. The codes typify NAS Y-MP solution techniques and represent the types of algorithms that automatic parallelizers must analyze and decompose. The straightforward, high-level domain decompositions employed for the explicit and SOR algorithms performed quite well. The implicit ADI algorithm required a new solver to reduce communication loads and a pipelined scheme to increase node utilization. The loop-level decomposition employed for the multigrid algorithm performed poorly. The major lesson taught by these manual transformations is that automatic tools must expose or utilize parallelism at a high level to create effective distributed memory codes. The postprocessor PAT utility assisted in disclosing reasons for less-than-expected parallel performance.