Capacitor mismatch caused by oxide thickness variations in submicron I. C. processes

摘要

Chip design in submicron processes will present new challenges and problems which were not present in designs with larger dimension processes. One effect in the newer processes is the field oxide thickness variation due to interconnect density variations. This effect becomes much more extreme for the smaller dimension processes. Large density discontinuities can cause lower yield and will also result in capacitor value mismatch over substantial distances from the edges of a large array when using poly/metal capacitors. If good matching in this type of large area capacitor array is required, the only way to achieve this is to guarantee nearly constant metal/ poly density for at least 1500 microns (this distance will likely depend on the process) around the edges of the array. If the array boundary is close to the chip edge, then dummy capacitors should be placed up to the chip edge, and another layout with similar density must be placed as close as possible to the relevant edges of the chip in the reticle. When using a standard MOSIS reticle size, this may entail placing dummy chip layouts around the chips of interest in order to guarantee that identical density exists for the required distance outside of any chip?s borders.