Quantitative Approach to Nonlinear IC Process Design Rule Scaling

摘要

This thesis introduces a methodology for determining scaled horizontal process design rule values that reach an effective tradeoff between not only cost and area, but performance. This is accomplished with a procedure that interactively finds the design rules that have the greatest impact on minimum layout area, and reduces them to their points of diminishing return from a cost, area, and performance perspective. The primary internment for performing this analysis is a process-independent RAM compiler. This thesis also describes optimization algorithms for exploring the large SRAM transistor size design space, and gives an innovative approach for optimizing an entire synchronous SRAM. Finally, a cost/benefit analysis of CGaAs transistor threshold voltage scaling is described. Through PUMA RAM compiler-based performance evaluations and die cost estimations, it was shown that CGaAs transistor threshold voltage scaling is expensive (with respect to expected benefits), compared to horizontal design rule scaling.