F-RISC- A 1.0 GOPS Fast Reduced Instruction Set Computer for Super Workstation and Teraops Parallel Processor Applications

摘要

The purpose of this contract has been to establish whether Heterojunction Bipolar Transistors or HBT's could be used in design of high clock rate digital computers. Additionally to establish whether HBT devices offer alternatives in case conventional COTS CMOS runs into manufacturing difficulty or fundamental device limitations below 0.1 microns minimum feature size. A demonstration GaAs HBT byteslice chipset for 2 GHz 1 GOPS Fast RISC computer has been fabricated.