Low-Power VLSI Architectures for Error Control Coding and Wavelets

摘要

This final report provides a brief summary of our research results supported by the above grant during the period from May 1,1998 to November 30, 2001. Our research has addressed design of high-speed, low-energy, low-area architectures for signal processing systems and error control coders. Contributions in the area of error control coding architectures include design of low-energy and low-complexity finite field arithmetic architectures and Reed- Solomon (RS) codecs. High- performance and low-power architectures for low- density parity-check (LDPC) codes have been developed.