Delivered Performance Predictions and Trends for RISC Processors in Radar Applications

摘要

Deployed radar and signal intelligence (SIGINT) systems require enormous amounts of real-time computational capability that must adhere to very confined power, weight and volume budgets. Computational requirements have been increasing as advanced adaptive signal processing techniques make their way from laboratories to deployed platforms. In many cases the computational requirements are increasing while power, weight and volume budgets are increasing only marginally if at all. These conflicting trends show an increase in processing requirements within existing platforms are driving physical and environmental budgets to ever higher levels of efficiency from commercial off- the-shelf (COTS) processing systems. This paper will address current trends in COTS processor designs and explore models that hopefully will predict how well these processors should perform per watt/kg/m(caret)3. The models will focus on space-time adaptive processing (STAP) and SIGINT processing requirements and how they map to very large-scale arrays of general-purpose programmable processors. System designers are currently examining various technology options for increasing the levels of sustainable performance per watt/kg/m(caret)3 for their applications. These options include fieldprogrammable gate arrays (FPGAs), alternative RISC processor architectures, and even a possible return to digital signal processor (DSP) devices. Each of these device classes has an associated cost of programmability, flexibility, upgradability, and interoperability with other devices. The question of efficiency of the device is not so easily stated, though, and is a function of the processing algorithms that must be performed as well as how well the devices can be interconnected in a large parallel processing system.