Failure Erasure Circuitry: A Duplicate Technique for Failure-Masking Systems

摘要

The purpose of the paper is to describe a redundancy technique which would require mere duplication to achieve the same failure-masking capabilities as von Neumann's triplication and majority-voting technique. An analysis of the circuit-failure problem is approached from the viewpoint of coding theory with comparisons made between the 'noisy channel' and 'circuit-failure' problems. Some of the difficulties of extrapolating from the former to the latter are discussed, as well as recent attempts to minimize the redundancy 'overhead' by coding over larger numbers of bits. Following a description of the binary erasure channel model, a proposal of a failure-erasure technique based upon it is outlined. The method enables failure-masking at duplicative rather than triplicative costs. There are constraints which this scheme imposes upon the circuit elements, however, and the characteristics of the ideal circuit element and logic signaling are proposed. The paper concludes with a discussion of existing hardware which approximates the desired characteristics. (Author)