EVALUATION OF INSTRUCTION SET PROCESSOR ARCHITECTURE BY PROGRAM TRACING

摘要

The thesis develops and evaluates methods for evaluation of the architecture of instruction set processors (ISPs). (An ISP is the logical processor defined by the instruction set, independent of physical implementation). The methods are based on analyzing traces of program executions which contain information about every instruction executed.nThe main advantages of the methods are:na) They permit a very detailed study of ISP behavior.nb) They are not restricted to specific languages or processors.nc) They are easily programmed.