Input Buffer Designs for a Radar Signal Processor.

摘要

Three Input Buffer designs which provide intermediate storage between the Analog to Digital Converters and the Digital Matched Filter of a Radar Signal Processor are presented. All desings use a basic all-ECL buffer module. Prototype hardware experiments indicate that with 8:1 input data multiplexing, ECL 10K technology will yield input rates up to 142 Ms/s per channel, and output rates of 45 Ms/s per convolver rail. (Author)