Fault Tolerant Spaceborne Computer Study. Preprocessor Design.

摘要

This report defines an architecture for a highly reliable spaceborne communications processor. The processor was to be designed to perform the demodulation, decoding, de-interleaving, interleaving, encoding, formatting and routine tasks anticipated for the Air Force Nuclear Forces Communications Satellite. The goal was to define a system having a long-term reliability comparable to that of the SAMSO Fault-Tolerant Spaceborne Computer and having a comparably low redundancy overhead. This technical report will be updated in the future to present a more detailed picture of the Wide Band Signal Processor. (Author)