An Investigation of Ordering, Tearing, and Latency Algorithms for the Time-Domain Simulation of Large Circuits.

摘要

Many circuit simulation programs have been available for the design of integrated circuits. However, these conventional circuit simulation programs calculate all of the node voltages or branch voltages and currents at each iteration and each timepoint. Even with sparse matrix techniques the simulation of modern large-scale integrated circuits is not possible in many situations due to the excessive computation time and high storage requirements. The goal of this research was to investigate new approaches to the simulation of integrated circuits which can alleviate the problems of excessive computation time and high storage requirements. A new ordering scheme for the modified nodal approach was developed, and some new algorithms, for the dc and transient analysis of logic circuits were studied. Different tearing methods and sparsity considerations for the node tearing method were theoretically and experimentally studied. Latency at the subcircuit and the network levels was investigated. Different latency criteria were proposed and studied. The result of this research is a new general purpose circuit simulation program SLATE. (Author)