Charge Sharing Models for MOS (Metal Oxide Semiconductors) Circuits

摘要

This paper addresses timing and glitch detection problems involving charge sharing in acyclic resistor capacitor networks. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. Our algorithms are intended for use in switch level simulators and timing verifiers which model transistors in digital VLSI designs as linear resistors. Computational complexity of our methods is also investigated. (Author)