Design for MISP: A Multiple Instruction Stream Shared Pipeline Processor

摘要

The Multiple Stream Shared Pipeline Processor is an eight-segment pipelined processor and is designed to allow eight essentially independent instruction streams to execute concurrently. This allows the hardware resources of the pipeline to be shared among the eight instruction streams. The basic hardware design for the MISP processor is presented. Methods for accomplishing process control are discussed and a description of the operating system is given. A mechanism for trap and interrupt handling is presented and the control structure is described. An appropriate system configuration is given for the MISP processor. The feasibility of a VLSI implementation of the MISP processor is evaluated. MISP has several advantages over a conventional microprocessor implementation. MISP has a higher pin utilization over a single processor, since it has one address bus and one bidirectional data bus which is shared by all of the processes. It also maximizes hardware resource utilization, since much of the hardware in the segments is shared and only the process state needs to be replicated for each process. Thus, for a modest cost increase, the MISP processor architecture achieves nearly an eight times speed-up over a conventional single stream microprocessor architecture. MISP represents a cost-effective alternative to conventional multiprocessor architectures.