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SIMP (Single Instruction Stream / Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture

机译：sImp（单指令流/多指令流水线）：一种新型高速单处理器架构

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Kazuaki Murakami; Naohiko Irie; Morihiro Kuga; Shinji Tomita;
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年度 1989
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1. Demonstration and architectural analysis of complementary metal-oxide semiconductor/multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing [J] . Jen-Ming Wu, Charles B. Kuznia, Bogdan Hoanca Applied optics . 1999,第11期

机译：用于单指令多数据并行流水线处理的互补金属氧化物半导体/多量子阱智能像素阵列细胞逻辑处理器的演示和体系结构分析
2. Reversible Systolic Arrays: M-ary Bijectivesingle-instruction Multiple-data (simd) Architectures And Their Quantum Circuits [J] . ANAS N. AL-RABADI Journal of Circuits, Systems, and Computers . 2008,第4期

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3. Flexible-length fast Fourier transform for mapping onto single-instruction multiple-data computing architecture [J] . K.J. Jones IEE proceedings, Part K. Vision, image and signal processing . 2006,第4期

机译：灵活长度的快速傅立叶变换，用于映射到单指令多数据计算体系结构
4. SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture [C] . Murakami, K., Irie, . 2001

机译：SIMP（单指令流/多指令流水线）：一种新型的高速单处理器架构
5. SYNCHRONOUS NETS FOR SINGLE INSTRUCTION STREAM - MULTIPLE DATA STREAM COMPUTERS [D] . KRYGIEL, ANNETTE JEAN. 1980

机译：单一指令流的同步网络-多数据流计算机
6. Learning Actions From Natural Language Instructions Using an ON-World Embodied Cognitive Architecture [O] . Ioanna Giorgi, Angelo Cangelosi, Giovanni L. Masala 2021

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7. Demonstration and architectural analysis of complementary metal-oxide semiconductor/multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing [O] . Wu JM 2012

机译：用于单指令多数据并行流水线处理的互补金属氧化物半导体/多量子阱智能像素阵列细胞逻辑处理器的演示和体系结构分析
8. Emulation Tool for Simulating Matrix Operations on an SIMD (Single Instruction Stream Multiple Data Stream) Multiprocessor [R] . Martin, H. L. 1987

机译：用于在sImD（单指令流多数据流）多处理器上模拟矩阵运算的仿真工具

SIMP (Single Instruction Stream / Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture

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