Implementation of a Language Analyzer for the Very High Speed Integrated Circuit Hardware Description Language

摘要

This thesis describes the incremental approach used to develop the first known C-base, UNIX-supported translator/analyzer for the Very High Speed integrated Circuit (VHSIC) Hardware Description Language (VHDL). This research consisted of defining a VHDL Intermediate Access (VIA) format as a translation target, dividing VHDL into manageable segments, describing VHDL-to-VIA relationships, designing software modules to create those relationships, and evaluating the functional and performance characteristics of the analyzer. The intermediate form, VIA, was based upon the Design Data Structure (DDS) developed by Alice Parker and David Knapp. Three of the nine VHDL language subsets identified were implemented in the language analyzer. In increments, these subsets were manually translated into specific examples of an enhanced version of DDS represented in a pile file format (VIA). These examples were then used as specifications for designing program modules to automatically translate VHDL code in VIA. After the program modules were written, these same examples were used as formal functional test specifications.