Formal Models of Hardware and Their Applications to VLSI Design Automation

摘要

This final report describes research in high-level synthesis, and an associated problem, area estimation of integrated circuits. The approach taken is to create formal models of the problem being solved. Four major research results have been produced. First, an accurate technique for estimation of integrated circuit layout area from cell information has been developed. Second, optimal clocking scheme synthesis has been automated. Third, programs to design pipelined and non-pipelined data paths have been developed. Fourth, register allocation of the data paths has also been automated. In addition, a representation for design information which was produced under a previous contract has been used for a number of applications. This research forms part of the ADAM Advanced Design Automation System under construction at the University of Southern California.