Complexities of Layouts in Three-Dimensional VLSI (Very Large-Scale Integration) Circuits

摘要

Recent advances in Very Large-Scale Integration (VLSI) fabrication technologies have demonstrated the feasibility of three-dimensional (3-D) circuits in a single chip. Due to the ability and flexibility to connect non-adjacent circuits using the third dimension, the cost of mapping non-planar circuits to two-dimensional (2-D) systems can be reduced. In this report, we examine the complexities in volume and maximum wire length of mapping circuits represented as undirected graphs to 3-D systems. Tighter bounds than those previously known are shown for various families of graphs, in both the one-active-layer and the unrestricted layouts. Finally, we develop a cost model to reflect the cost implementation in the third dimension and present an optimization model on the number of layers to minimize the overall cost.