Modeling, Simulation and Comparison of Interconnection Networks for Parallel Processing

摘要

This thesis extends existing modeling, analysis and comparison of interconnection networks for parallel processing systems. Simulation models are developed for the multistage cube network, the single stage cube network (hypercube), and the Illiac IV mesh-type network. They are then used to provide a comparison of three classes of interconnection networks which, until now, has not been performed. These models implemented using a commercially packaged simulation language provide for compact source code and ease of readability. The networks are modeled under a common set of operating assumptions and system environment. This allows for accurate comparisons of average network packet delays an memory requirements necessary to physically implement the chosen network at a given network operating load. It is concluded that, for the network sizes and operating conditions established, the multistage cube network performs better at a lower hardware cost than do the single stage cube and mesh networks. As a result, the designer of a parallel processing system is given additional insight for choosing an interconnection network which best suits the application needs.