New Multi-Decoder PLA (Programmable Logic Array) Design

摘要

A multi-decoder design for Programmable Logic Array devices is introduced and found to be both two decoder ROM and single decoder PLA devices in implementing a special class of Boolean expressions. In this class, the logic expressions may be lengthy but are restricted in the number of input variables comprising each p-term. A theoretical analysis of the area efficiency of the new design is supplemented by CAD design examples which verify its superiority. Implementation of the multi-decoder design using three dimensional microcircuit topography to attain even greater savings in area and speed is considered in the conclusion of this report.