Multiple-Valued Logic System for Circuit Extraction to VHDL 1076-1987

摘要

Multiple-valued logic is a topic of concern for modeling standards in the VHSIC Hardware Description Language, VHDL 1076-1987. With the various forms of layout styles in MOS devices there exist different strengths of electrical signals propagated throughout a circuit. Additionally, logic extraction to VHDL of VLSI layout designs may contain left over transistors that must be modeled correctly in VHDL. A multiple-valued logic system can adequately model signals with different strengths as well as conflicts between signal values. Once a multiple-valued logic system is defined, a logic extraction system may then produce VHDL for hardware component representations down to the transistor level. The goal of this thesis is to present a ten-level multiple-valued logic system and provide a Prolog-based logic extraction tool for generation of VHDL from a transistor net list. The Prolog-based logic extraction system will also provide groundwork for further research in the area of formal verification with VHDL. Various tools using symbolic representations and multiple-valued logic are essential in a CAD environment where logic extraction from layout to VHDL is incorporated into validation and verification. Theses. (RH)