首页> 外国专利> MULTIPLE-VALUED LOGIC CIRCUIT ARCHITECTURE: SUPPLEMENTARY SYMMETRICAL LOGIC CIRCUIT STRUCTURE (SUS-LOC)

MULTIPLE-VALUED LOGIC CIRCUIT ARCHITECTURE: SUPPLEMENTARY SYMMETRICAL LOGIC CIRCUIT STRUCTURE (SUS-LOC)

机译:多值逻辑电路体系结构:辅助对称逻辑电路结构(SUS-LOC)

摘要

Circuit structure and resulting circuitry formultiple-valued logic. The circuit structure allows the design andfabrication of any r-valued logic function of n-places wherer is an integer greater than I and n is an integer greaterthan 0. This structure is called SUpplementary SymmetricalLOgic Circuit structure (SUS-LOC). In circuits incorporatingSUS-LOC, circuit branches are realized that uniquely delivercircuit response and output. For some circuits, and due tothe operating characteristics of the switch elements, additionalcircuit elements, or stages, must be incorporated to prevent"back biasing". SUS-LOC is fully active. Only activeelements perform logic synthesis and those components notdirectly related to logic synthesis, such as resistors and/orother passive loads, are relegated the task of circuit protection.The fabrication of r-valued, multi-valued, or multiple-valuedlogic circuits, designed using the definitions of the SUS-LOCstructure can be accomplished with known techniques,materials, and equipment.
机译:用于的电路结构和所得电路多值逻辑。电路结构允许设计和n位的任何r值逻辑函数的制造,其中r是大于I的整数,而n是大于I的整数大于0。此结构称为辅助对称LOgic电路结构(SUS-LOC)。在电路合并中SUS-LOC,实现了独特的电路分支电路响应和输出。对于某些电路,由于开关元件的操作特性,附加必须合并电路元件或级,以防止“反向偏向”。 SUS-LOC已完全激活。仅活动元素执行逻辑综合,而那些组件不执行与逻辑综合直接相关,例如电阻和/或其他无源负载则降级为电路保护的任务。r值,多值或多值的制造逻辑电路,使用SUS-LOC的定义进行设计结构可以用已知技术完成,材料和设备。

著录项

  • 公开/公告号CA2333623C

    专利类型

  • 公开/公告日2009-12-22

    原文格式PDF

  • 申请/专利权人 OLSON EDGAR DANNY;

    申请/专利号CA19992333623

  • 发明设计人 OLSON EDGAR DANNY;

    申请日1999-05-21

  • 分类号H03K19/094;H03K19;

  • 国家 CA

  • 入库时间 2022-08-21 18:42:53

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