Specification and Equivalence Verification of Sequential Circuits via VHDL.

摘要

This research presents a merger of the specification and design capabilities of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) with a known verification method (UC Berkeley's verify software) in order to solve the design and verification problem of sequential circuits. The fruits of this research are a behavioral VHDL model for sequential circuit specification, a structural VHDL model for sequential circuit design, and a method for comparing two circuits described using these VHDL models in order to demonstrate circuit equivalence. The behavioral and structural VHDL models were developed and tested within the Intermetric's VHDL software support environment. Modifications were made to the existing UC Berkeley verify software so that it could accept sequential circuits described using the structural VHDL model. Additionally, a behavioral to structural VHDL translator (b2s) was developed such that sequential circuits expressed in the behavioral VHDL model could be shown equivalent to structural VHDL designs via the UC Berkeley verification software.