Design and Implementation of a Read Prediction Buffer.

摘要

Cache memories, which are the level of memory between the CPU and the main memory, hold small amounts of data and instructions, and allow the CPU to access the contents in them very quickly. This significantly reduces the read access time for the CPU if the required information is available in the cache. However, caches are small and can only hold the most commonly used data and instructions required by the CPU. When information requested does not appear in the cache, a 'cache miss' occurs and the CPU must fetch the required data from the main memory. The Read Prediction Buffer reduces this time-costly read access by attempting to predict the possible miss address, and pre-fetch the read data.... VLSI (Very Large Scale Integration) design, Memory address prediction, Dynamic ram, MAGIC, CMOS, Cache performance improvement.