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Design, implementation and performance evaluation of an MDFE read channel

机译:MDFE读取通道的设计,实现和性能评估

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A 100 Mb/s (1,7) MDFE (multi-level decision feedback equalization) read channel has been designed, prototyped, and tested on a spinstand. It is made up of an analog forward equalizer consisting of two biquads, a comparator, a feedback equalizer consisting of 6 taps plus an analog exponential decay circuit, timing/gain/dc-offset control circuits, an analog PLL and VCO, and VGA. An analytical technique has been developed for equalizer design. It incorporates certain key constraints for reducing hardware complexity as well as error propagation. The measured bit-error-rate and off-track performance demonstrate the robustness of the equalizer over a broad range of user densities. The experimental results confirm that MDFE is a viable signal detection technique for achieving high density and high data rate magnetic recording.
机译:已经设计了100 Mb / s(1,7)MDFE(多级判决反馈均衡)读取通道,并在自旋支架上对其进行了原型测试。它由一个由两个双二阶组成的模拟正向均衡器,一个比较器,一个由6个抽头组成的反馈均衡器,一个模拟指数衰减电路,定时/增益/直流偏移控制电路,一个模拟PLL和VCO以及VGA组成。已经开发出一种用于均衡器设计的分析技术。它合并了某些关键约束,以降低硬件复杂性以及错误传播。测得的误码率和轨外性能证明了均衡器在广泛的用户密度范围内的稳健性。实验结果证实,MDFE是实现高密度和高数据率磁记录的可行信号检测技术。

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