Very High-Speed Arithmetic Processors (The Gauss Machine).

摘要

Our VHSAP ARO study has lead to a number of accomplishments including an original VLSI processor and a system with a high residue number system (RNS) content called the Gauss Machine. The Gauss machine is a SIMD systolic array architecture which takes advantage of the Galois-enhanced quadratic residue number system (GEQRNS) to form reduced complexity arithmetic elements. The Gauss machine is targeted at front-end signal and image processing applications. With a 2x2 array of GEQRNS multiplier accumulators operating at 10 MHz, the Gauss machine can achieve a peak equivalent throughput of 320 million operations per second when performing complex arithmetic. The Gauss machine is designed for a broader, more general class of problems other than RNS based systems which have been constructed: the Gauss machine may be used to accelerate computations which involve or may be expressed as matrix-matrix (level 3), matrix-vector (level 2), or vector-vector (level l) operations. This paper describes the implementation of the Gauss machine and how it may be used to accelerate signal processing operations.